SI5364 Datasheet, PDF (34/40 Pages) Silicon Laboratories – SONET/SDH PRECISION PORT CARD CLOCK IC

Si5364
Pin #
Pin Name
Table 10. Pin Descriptions (Continued)
I/O
Signal Level
Description
C3
INCDELAY
I*
LVTTL
Increment Output Phase Delay.
The INCDELAY and DECDELAY pins can adjust the
phase of the Si5364 clock outputs. Adjustment is
accomplished by driving a pulse (a transition from
low to high and then back to low) into one of the pins
while the other pin is held at a logic low level.
Each pulse on the INCDELAY pin adds a fixed delay
to the Si5364’s clock outputs. The fixed delay time is
equal to twice the period of the 622 MHz output clock
(t_DELAY = 2/f_{o_622}). The frequency of the 622 MHz
output clock (f_{o_622}) is nominally 32x the frequency of
the input clock. The frequency of the 622 MHz output
clock (fo_622) is scaled additionally according to the
setting of the FEC[1:0] pins.
When the phase of the Si5364 clock outputs is
adjusted using the INCDELAY and/or DECDELAY
pins, the output clock moves to its new phase setting
at a rate of change that is determined by the setting
of the BWSEL[1:0] pins.
Note: INCDELAY is ignored when the Si5364 is operating
in digital hold (DH) mode.
C4
DECDELAY
I*
LVTTL
Decrement Output Phase Delay.
The INCDELAY and DECDELAY pins can adjust the
phase of the Si5364 clock outputs. Adjustment is
accomplished by driving a pulse (a transition from
low to high and then back to low) into one of the pins
while the other pin is held at a logic low level.
Each pulse on the DECDELAY pin removes a fixed
delay from the Si5364’s clock outputs. The fixed
delay time is equal to twice the period of the 622
MHz output clock (t_DELAY = 2/f_{o_622}). The frequency
of the 622 MHz output clock (f_{o_622}) is nominally 32x
the frequency of the input clock. The frequency of the
622 MHz output clock (fo_622) is scaled additionally
according to the setting of the FEC[1:0] pins.
When the phase of the Si5364 clock outputs is
adjusted using the INCDELAY and/or DECDELAY
pins, the output clock moves to its new phase setting
at a rate of change that is determined by the setting
of the BWSEL[1:0] pins.
Note: INCDELAY is ignored when the Si5364 is operating
in digital hold (DH) mode.
*Note: The LVTTL inputs on the Si5364 device have an internal pulldown mechanism that causes the input to default to a logic
low state if the input is not driven from an external source.
34
Rev. 2.2