SI5100 Datasheet, PDF (34/40 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

Si5100
Pin Number(s)
M9
Name
TXMSBSEL
L3
TXREXT
M12
TXSQLCH
E5–10, F5–10,
G5–10, H5–10,
J5–10, K5–10
H3
V_DD
V_DDIO
C5
VREF
I/O Signal Level
Description
I
LVTTL Transmit Data Bus Bit Order Select.
This input determines the order in which data
bits received on the TXDIN[15:0] bus are trans-
mitted on the high-speed serial output TXDOUT.
For TXMSBSEL = 0, data on TXDIN0 is trans-
mitted first followed by TXDIN1 through
TXDIN15 (TXDIN1 through TXDOUT3 if
MODE16 = 0).
For TXMSBSEL = 1, TXDIN15 (TXDIN3) is
transmitted first followed by TXDIN14 (TXDIN2)
through TXDIN0.
Note: This input has an internal pulldown.
Transmitter External Bias Resistor.
This resistor is used by the transmitter circuitry
to establish bias currents within the device. This
pin must be connected to GND through a
3.09 kΩ (1%) resistor.
I
LVTTL Transmit Data Squelch.
When TXSQLCH is set low, the output data
stream on TXDOUT is forced to a zero state. Set
TXSQLCH high for normal operation.
The TXSQLCH input is ignored when operating
in line loopback mode (LLBK = 0).
Note: This input has an internal pullup.
V_DD
1.8 V
Supply Voltage.
Nominally 1.8 V.
V_DDIO
O
1.8 V or 3.3 V
Voltage Ref
LVTTL I/O Supply Voltage.
Connect to either 1.8 or 3.3 V. When connected
to 3.3 V, LVTTL compatible voltage swings are
supported on the LVTTL inputs and LVTTL out-
puts of the device.
Voltage Reference.
The Si5100 provides an output voltage reference
that can be used by an external circuit to set the
LOS threshold, slicing level, or sampling phase
adjustment. The equivalent resistance between
this pin and GND should not be less than 10 kΩ.
The reference voltage is nominally 1.25 V.
34
Rev. 1.1