SI5100 Datasheet, PDF(10/40 Page) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

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SI5100 Datasheet, PDF (10/40 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

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Si5100

Table 5. AC Characteristics (Receiver PLL)1

(VDD = 1.8 V Â± 5%, TA = â20 to 85 Â°C)

Parameter

Symbol

Jitter Tolerance

JTOL(PP)

(RXDIN = 100 mVPPD, PRBS31)2

Test Condition

f = 10 â 600 Hz

f = 0.6 â 6 kHz

f = 6 â 100 kHz

f = 100 kHzâ1 MHz

f = 1â20 MHz

Acquisition Time

Input Reference Clock Frequency

(REFSEL = 1)

TAQ

RCFREQ

REFRATE = 1

REFRATE = 0

Reference Clock Duty Cycle

RCDUTY

Reference Clock Frequency

Tolerance

RCTOL

Frequency Difference at which

LOL

Receive PLL goes out of Lock

(REFCLK compared to the

divided down VCO clock)

Frequency Difference at which

Receive PLL goes into Lock

(REFCLK compared to the

divided down VCO clock)

LOCK

Notes:

1. Bellcore specifications: GR-253-CORE, Issue 3, September 2000.

2. Instrument limited.

Min Typ

152

0.4

0.3

155

â100

610

732

Max

169

84.4

100

Unit

UIPP

MHz

ppm

860 ppm

366

240 ppm

Rev. 1.1

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