SI5100 Datasheet, PDF (30/40 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

Si5100
Pin Number(s)
G13
H13
E14
F14
E13
F13
C14
D14
C13
D13
A14
B14
B12
B13
A12
A13
B10
B11
A10
A11
B8
B9
A8
A9
B6
B7
A6
A7
B4
B5
A4
A5
F3
Name
RXDOUT15+
RXDOUT15–
RXDOUT14+
RXDOUT14–
RXDOUT13+
RXDOUT13–
RXDOUT12+
RXDOUT12–
RXDOUT11+
RXDOUT11–
RXDOUT10+
RXDOUT10–
RXDOUT9+
RXDOUT9–
RXDOUT8+
RXDOUT8–
RXDOUT7+
RXDOUT7–
RXDOUT6+
RXDOUT6–
RXDOUT5+
RXDOUT5–
RXDOUT4+
RXDOUT4–
RXDOUT3+
RXDOUT3–
RXDOUT2+
RXDOUT2–
RXDOUT1+
RXDOUT1–
RXDOUT0+
RXDOUT0–
RXLOL
I/O Signal Level
Description
O
LVDS
Differential Parallel Receive Data Output.
The data recovered from the signal present on
RXDIN is demultiplexed and output as a 16-bit
parallel word via RXDOUT[15:0]. The bit order
for demultiplexing is selected by the RXMSBSEL
input. The RXDOUT[15:0] outputs are aligned to
the rising edge of RXCLK1.
O
LVTTL Receiver Loss-of-Lock.
This output is asserted (driven low) when the
recovered clock frequency deviates from the ref-
erence clock by the amount specified in Table 5
on page 10 (LOL).
30
Rev. 1.1