SI5100 Datasheet, PDF (14/40 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

Si5100
4. Functional Description
The Si5100 transceiver is a low-power fully-integrated
serializer/deserializer that provides significant margin to
all SONET/SDH jitter specifications. The device
operates from 2.41–2.7 Gbps making it suitable for OC-
48/STM-16 applications and OC-48/STM-16
applications that use 255/238 or 255/237 forward error
correction (FEC) coding. The low-speed
receive/transmit interface uses a low-power parallel
LVDS interface compatible with LVPECL.
5. Receiver
The receiver within the Si5100 includes a precision
limiting amplifier, a jitter-tolerant clock and data
recovery unit (CDR), and a 1:16 demultiplexer.
Programmable data slicing level and sampling phase
adjustment are provided to support bit-error-rate (BER)
optimization for long-haul applications.
The receiver signal amplitude monitoring circuit is also
used in the generation of the loss-of-signal alarm (LOS).
5.2.2. Loss-of-Signal Alarm (LOS)
The Si5100 can be configured to activate a loss-of-
signal alarm output (LOS) when the RXDIN input
amplitude drops below a programmable threshold level.
An appropriate level of hysteresis prevents unnecessary
switching on LOS.
The LOS threshold level is set by applying a dc voltage
to the LOSLVL input. The mapping of the voltage on the
LOSLVL pin to the LOS threshold level depends on the
state of the SLICEMODE input. (The SLICEMODE input
is used to select either absolute slice mode or
proportional slice mode operation.)
The LOSLVL mapping for absolute slice mode
(SLICEMODE = 0) is given in Figure 4. The linear
region of the assert can be approximated by the
following equation:
5.1. Receiver Differential Input Circuitry
The receiver serial input provides proper termination
and biasing through two resistor dividers internal to the
device. The active circuitry has high-impedance inputs
and provides sufficient gain for the clock and data
recovery unit to recover the serial data. The input bias
levels are optimized for jitter tolerance and input
sensitivity and are typically not dc compatible with
standard I/Os; simply ac couple the data lines as shown
in Figure 10 on page 22.
5.2. Limiting Amplifier
The Si5100 incorporates a limiting amplifier with
sufficient gain to directly accept the output of
transimpedance amplifiers.
The limiting amplifier provides sufficient gain to fully
saturate with input signals that are greater than 30 mV
peak-to-peak differential. In addition, input signals up to
2 V peak-to-peak differential do not cause any
performance degradation.
5.2.1. Receiver Signal Amplitude Monitoring
The Si5100 limiting amplifier includes circuitry that
monitors the amplitude of the receiver differential input
signal (RXDIN). The RXAMPMON output provides an
analog output signal that is proportional to the input
signal amplitude. The signal is enabled when slice
mode is asserted. The voltage on the RXAMPMON
output is nominally equal to one-half of the differential
peak-to-peak signal amplitude of RXDIN as shown in
Equation 1:
V_RXAMPMON ≈ V_RXDIN(PP) × .566
Equation 1
V_LOS ≈ V_LOSLVL × .958
Equation 2
where V_LOS is the differential PK-PK LOS threshold
referred to the RXDIN input, and V_LOSLVL is the voltage
applied to the LOSLVL pin.
The linear region of the de-assert curve can be
approximated by the following equation:
V_LOS ≈ V_LOSLVL × .762
Equation 3
The LOSLVL mapping for proportional slice mode
(SLICEMODE = 1) is given in Figure 6 on page 17. The
linear region of the assert can be approximated by the
following equation:
V_LOS ≈ V_LOSLVL × .61
Equation 4
where V_LOS is the differential pk–pk LOS threshold
referred to the RXDIN input, and V_LOSLVL is the voltage
applied to the LOSLVL pin.
The linear region of the de-assert curve can be
approximated by the following equation:
V_LOS ≈ V_LOSLVL × .72
Equation 5
The LOS detection circuitry is disabled by tieing the
LOSLVL input to VREF. This forces the LOS output
high.
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Rev. 1.1