SI5100 Datasheet, PDF (1/40 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

Si5100
SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER
Features
Complete, low-power, high-speed, SONET/SDH transceiver with
integrated limiting amp, CDR, CMU, and MUX/DEMUX
Data rates supported:
SONET-compliant loop timed
OC-48/STM-16 through 2.7 Gbps operation
FEC
Programmable slicing level and
Low-power operation 1.2 W (typ) sample phase adjustment
DSPLL™ based clock multiplier
unit w/ selectable loop filter
LVDS/LVPECL compatible
interface
bandwidths
Single supply 1.8 V operation
Integrated limiting amplifier
15 x 15 mm BGA package
Loss-of-signal (LOS) alarm
Diagnostic and line loopbacks
Applications
SONET/SDH transmission
systems
Optical transceiver modules
SONET/SDH test equipment
Description
The Si5100 is a complete low-power transceiver for high-speed serial
communication systems operating between OC-48 and 2.7 Gbps. The receive
path consists of a fully-integrated limiting amplifier, clock and data recovery unit
(CDR), and 1:16 deserializer. The transmit path combines a low-jitter clock
multiplier unit (CMU) with a 16:1 serializer. The CMU uses Silicon Laboratories’
DSPLL technology to provide superior jitter performance while reducing design
complexity by eliminating external loop filter components. To simplify BER
optimization in long-haul applications, programmable slicing and sample phase
adjustment are supported. The Si5100 operates from a single 1.8 V supply over
the industrial temperature range (–20 to 85 °C).
Functional Block Diagram
SLICELVL
PHASEADJ
RXDIN
Limiting
AMP
TXDOUT
CDR
Line
Loopback
Diagnostic
Loopback
÷
RXDOUT[15:0]
RXCLK
TXDIN[15:0]
Si5100
Bottom View
Ordering Information:
See page 35.
TXCLKOUT
DSPLL^TM
TX CMU
BWSEL[1:0]
TXCLK16IN
REFCLK
Rev. 1.1 7/04
Copyright © 2004 by Silicon Laboratories
Si5100