SI5100 Datasheet, PDF (16/40 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

Si5100
than the amount specified in Table 5 on page 10.
The RXLOL output is asserted automatically if a valid
reference clock is not detected.
The RXLOL output is also asserted whenever the loss
of signal alarm (LOS) is active, provided that the LTR
input is set high (i.e. provided that the device is not
configured for lock-to-reference mode).
5.3.3. Lock-to-Reference
The lock-to-reference (LTR) input can be utilized to
ensure the presence of a stable output clock during a
loss-of-signal alarm (LOS). When LTR is asserted, the
CDR is prevented from phase locking to the data signal
and the CDR locks the RXCLKOUT1 and RXCLKOUT2
outputs to the reference clock. In typical applications,
the LOS output is tied to the LTR input to force a stable
output clock during a loss-of-signal condition.
5.4. Deserialization
The Si5100 deserializes the high-speed data from the
CDR and outputs the deserialized data on the 16-bit
parallel data bus RXDOUT[15:0]. The demultiplexer
used for deserialization is configured by the MODE16
pin to output either 4-bit or 16-bit data words on the bus.
The data words are output on RXDOUT[15:0] with the
rising edge of RXCLK1. When the demultiplexer is
configured to output 4-bit data words, the data is output
on RXDOUT[3:0].
5.4.1. Serial Input to Parallel Output Relationship
The Si5100 provides the capability to select the order in
which the received serial data is mapped to the parallel
output bus RXDOUT[15:0]. The mapping of the receive
bits to the output data word is controlled by the
RXMSBSEL input. When RXMSBSEL is set low, the
first bit received is output on RXDOUT0, and the
following bits are output in order on RXDOUT1 through
RXDOUT15 (RXDOUT1 through RXDOUT3 if
MODE16 = 0). When RXMSBSEL is set high, the first
bit received is output on RXDOUT15 (RXDOUT3), and
the following bits are output in order on RXDOUT14
(RXDOUT2) through RXDOUT0.
5.5. Voltage Reference Output
The Si5100 provides an output voltage reference that
can be used by external circuitry to set the LOS
threshold, slicing level, or sampling phase adjustment
input voltage levels. One possible implementation uses
a resistor divider to set the control voltage for the
LOSLVL, SLICELVL, or PHASEADJ inputs. An
alternative is the use of a digital-to-analog converters
(DACs) to set the control voltages. With this approach,
VREF is used to set the range of the DAC outputs. The
voltage on the VREF output is nominally 1.25 V.
350
300
250
200
150
100
= ^{.958 LOSLVL}
V ^LOS
= ^{.762 LOSLVL}
V LOS
Assert
DeAssert
50
0
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
LOSLV (V)
Figure 4. Typical LOSLVL Transfer Curve, Absolute Slice Mode (SLICEMODE = 0)
16
Rev. 1.1