SI5100 Datasheet, PDF (32/40 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

Si5100
Pin Number(s)
Name
I/O Signal Level
Description
P2
TXCLK16OUT+
O
LVDS
Divided Down Transmit Output Clock.
P1
TXCLK16OUT–
This clock output is generated by dividing down
the high-speed output clock, TXCLKOUT, to
match the TXDOUT[15:0] word rate. This is
accomplished by dividing by either 4 or 16,
depending on the state of the MODE16 input.
The TXCLK16OUT is provided for use in counter
clocking schemes that transfer data between the
system framer and the Si5100. (See REFSEL
and REFRATE descriptions.)
K12
TXCLKDSBL
I
LVTTL High-Speed Transmit Clock Disable.
When this input is high, the output driver for
TXCLKOUT is disabled. In applications that do
not require the output data clock, the output
clock driver should be disabled to save power.
Note: This input has an internal pulldown.
G1
TXCLKOUT+
O
CML
High-Speed Transmit Clock Output.
H1
TXCLKOUT–
The high-speed output clock, TXCLKOUT, is
generated by the PLL in the clock multiplier unit.
Its frequency is nominally 16 or 32 times the
selected reference source.
32
Rev. 1.1