SI5100 Datasheet, PDF (24/40 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

Si5100
16. Si5100 Pinout: 195 BGA
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RX
RX
[10]+
[8]–
[8]+
[6]–
[6]+
[4]–
[4]+
[2]–
[2]+
[0]–
[0]+ CLK[1]– CLK[1]+
A
RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RX
RX
[10]–
[9]–
[9]+
[7]–
[7]+
[5]–
[5]+
[3]–
[3]+
[1]–
[1]+ CLK[2]– CLK[2]+
GND
B
RXDOUT RXDOUT
[12]+
[11]+
RXCLK2
DIV
RXREXT
RXAMP
MON
RXSQLCH
RXCLK2
DSBL
RSVD_
GND
RSVD_
GND
VREF SLICELVL LOSLVL
GND
GND
C
RXDOUT RXDOUT RXMSB
[12]–
[11]–
SEL
GND
GND
GND
GND
GND
GND
GND
PHASEADJ
RSVD_
GND
GND
RXDIN+
D
RXDOUT RXDOUT SLICE
[14]+
[13]+ MODE
GND
VDD
VDD
VDD
VDD
VDD
VDD
GND
LTR
GND RXDIN–
E
RXDOUT RXDOUT
[14]–
[13]–
DLBK
GND
VDD
VDD
VDD
VDD
VDD
VDD
RXCLKI-
DSBL
RXLOL
GND
GND
F
REF
CLK+
RXDOUT
[15]+
MODE16
GND
VDD
VDD
VDD
VDD
VDD
VDD RESET LOS
GND TXCLKOUT+
G
REF
CLK-
RXDOUT
[15]–
LLBK
GND
VDD
VDD
VDD
VDD
VDD
VDD REFRATE VDDIO GND TXCLKOUT– _H
TXDIN TXDIN
[14]+
[15]+
LPTM
GND
VDD
VDD
VDD
VDD
VDD
VDD
GND
GND
GND
GND
J
TXDIN TXDIN TXCLK
[14]–
[15]–
DSBL
GND
VDD
VDD
VDD
VDD
VDD
VDD
RSVD_
GND
FIFOERR
GND
TXDOUT+
K
TXDIN
[12]+
TXDIN
[13]+
REFSEL
GND
GND
GND
GND
GND
GND
GND
RSVD_ _{TXREXT GND TXDOUT–}
GND
L
TXDIN
[12]–
TXDIN
[13]–
TXSQLCH
RSVD_
GND
BWSEL1
TXMSB
SEL
RSVD_
GND
BWSEL0 FIFORST
TXLOL
GND
GND
GND
GND
M
TXDIN
[11]+
TXDIN
[11]–
TXDIN
[9]+
TXDIN TXDIN
[9]–
[7]+
TXDIN
[7]–
TXDIN
[5]+
TXDIN
[5]–
TXDIN
[3]+
TXDIN
[3]–
TXDIN
[1]+
TXDIN TXCLK16 TXCLK16
[1]–
IN+
IN–
N
TXDIN
[10]+
TXDIN
[10]–
TXDIN
[8]+
TXDIN TXDIN
[8]–
[6]+
TXDIN
[6]–
TXDIN
[4]+
TXDIN
[4]–
TXDIN
[2]+
TXDIN
[2]–
TXDIN
[0]+
TXDIN TXCLK16 TXCLK16
[0]–
OUT+ OUT–
P
Figure 13. Si5100 Pin Configuration (Bottom View)
24
Rev. 1.1