SI5100 Datasheet, PDF (25/40 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

Si5100
1
2
3
4
5
6
7
8
9
10
11
12 13
14
RX
RX RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT
A
CLK[1]+ CLK[1]– [0]+
[0]–
[2]+
[2]–
[4]+
[4]–
[6]+
[6]–
[8]+
[8]–
[10]+
B
GND
RX
RX RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT
CLK[2]+ CLK[2]– [1]+
[1]–
[3]+
[3]–
[5]+
[5]–
[7]+
[7]–
[9]+
[9]–
[10]–
C
GND
GND
LOSLVL SLICELVL VREF
RSVD_
GND
RSVD_
GND
RXCLK2
DSBL
RXSQLCH
RXAMP
MON
RXREXT
RXCLK2
DIV
RXDOUT RXDOUT
[11]+
[12]+
D
RXDIN+ GND
RSVD_ PHASE
GND
ADJ
GND
GND
GND
GND
GND
GND
GND
RXMSB RXDOUT RXDOUT
SEL
[11]–
[12]–
E
RXDIN– GND
LTR
GND
VDD
VDD
VDD
VDD
VDD
VDD
GND
SLICE RXDOUT RXDOUT
MODE [13]+
[14]+
F
GND
GND
RXLOL
RXCLK1
DSBL
VDD
VDD
VDD
VDD
VDD
VDD
GND
DLBK
RXDOUT RXDOUT
[13]–
[14]–
G
TXCLKOUT+ GND
LOS RESET VDD
VDD
VDD
VDD
VDD
VDD
GND
MODE16
RXDOUT
[15]+
REF
CLK+
H
TXCLKOUT– GND VDDIO REFRATE VDD
VDD
VDD
VDD
VDD
VDD
GND
LLBK
RXDOUT REF
[15]–
CLK–
J
GND
GND
GND
GND
VDD
VDD
VDD
VDD
VDD
VDD
GND
LPTM
TXDIN TXDIN
[15]+
[14]+
K
TXDOUT+ GND
FIFOERR
RSVD_
GND
VDD
VDD
VDD
VDD
VDD
VDD
GND
TXCLK TXDIN TXDIN
DSBL [15]–
[14]–
L
TXDOUT– GND
TXREXT
RSVD_
GND
GND
GND
GND
GND
GND
GND
GND
REFSEL
TXDIN
[13]+
TXDIN
[12]+
M
GND
GND
GND
GND
TXLOL
FIFORST BWSEL0
RSVD_
GND
TXMSB
SEL
BWSEL1
RSVD_
GND
TXSQLCH
TXDIN
[13]–
TXDIN
[12]–
N
TXCLK16 TXCLK16 TXDIN TXDIN TXDIN TXDIN TXDIN TXDIN TXDIN TXDIN TXDIN TXDIN TXDIN TXDIN
IN–
IN+
[1]–
[1]+
[3]–
[3]+
[5]–
[5]+
[7]–
[7]+
[9]–
[9]+
[11]–
[11]+
P
TXCLK16 TXCLK16 TXDIN TXDIN TXDIN TXDIN TXDIN TXDIN TXDIN TXDIN TXDIN TXDIN TXDIN TXDIN
OUT– OUT+
[0]–
[0]+
[2]–
[2]+
[4]–
[4]+
[6]–
[6]+
[8]–
[8]+
[10]–
[10]+
Figure 14. Si5100 Pin Configuration (Transparent Top View)
Rev. 1.1
25