SI5100 Datasheet, PDF (27/40 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

Pin Number(s)
J12
Name
LPTM
E3
LTR
G12
MODE16
D4
PHASEADJ
G14
REFCLK+
H14
REFCLK–
Si5100
I/O Signal Level
Description
I
LVTTL Loop Timed Operation.
When this input is set low, the recovered clock
from the receiver is divided down and used as
the reference source for the transmit CMU. The
narrowband setting for the DSPLL CMU is suffi-
cient to provide SONET compliant jitter genera-
tion and jitter transfer on the transmit data and
clock outputs (TXDOUT,TXCLKOUT). Set this
pin high for normal operation.
Note: This input has an internal pullup.
I
LVTTL Lock-to-Reference.
When the LTR input is set low, the receiver PLL
locks to the selected reference clock. This func-
tion can be used to force a stable output clock on
the RXCLK1 and RXCLK2 outputs when no valid
input data signal is applied to RXDIN.
When the LTR input is set high, the receiver PLL
locks to the RXDIN signal (normal operation).
Note: This input has an internal pullup.
I
LVTTL MUX/DEMUX Mode.
This input configures the multiplexer/demulti-
plexer to operate with either 4-bit or 16-bit paral-
lel data words. When this input is set high, the
device is configured for 16-bit parallel word
transfers on RXDOUT[15:0] and TXDIN[15:0].
When this input is set low, the multiplexer/demul-
tiplier operates with 4-bit word transfers on RXD-
OUT[3:0] and TXDIN[3:0].
I
Sampling Phase Adjust.
Applying an analog voltage to this pin allows
adjustment of the sampling phase across the
data eye. Tieing this input to VREF nominally
centers the sampling phase.
I
LVPECL Differential Reference Clock.
This input is used as the Si5100 reference clock
when the REFSEL input is set high
(REFSEL = 1). The reference clock sets the
operating frequency of the Si5100 transmit
CMU, which is used to generate the high-speed
transmit clock TXCLKOUT. The reference clock
is also used by the Si5100 receiver CDR to cen-
ter the PLL during lock acquisition, and as a ref-
erence for determination of the receiver lock
status.
The REFCLK frequency is either 1/16th or
1/32nd of the serial data rate (nominally 155 or
78 MHz, respectively). The REFCLK frequency
is selected using the REFRATE input.
Rev. 1.1
27