SI5100 Datasheet, PDF (29/40 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

Si5100
Pin Number(s)
Name
I/O Signal Level
Description
B2
RXCLK2+
O
LVDS
Differential Receiver Clock Output 2.
B3
RXCLK2–
An auxiliary output clock is provided on this pin
that is equivalent to, or a submultiple of, the out-
put word rate. The divide factor used in generat-
ing RXCLK2 is set via RXCLK2DIV.
C12
RXCLK2DIV
I
F4
RXCLK1DSBL
I
LVTTL
LVTTL
RXCLK2 Clock Divider Select.
This input selects the divide factor used to gen-
erate the RXCLK2 output. When this input is
driven high, RXCLK2 is equal to the output word
rate on RXDOUT. When driven low, RXCLK2 is
1/4th the output word rate.
Note: This input has an internal pullup.
RXCLK1 Disable.
Setting this input low disables the RXCLK1 output.
This is used to save power in applications that do not
require the primary output clock.
Note: This input has an internal pullup.
C8
RXCLK2DSBL
I
LVTTL RXCLK2 Disable.
Setting this input low disables the RXCLK2 out-
put. This saves power in applications that do not
require an auxiliary clock.
Note: This input has an internal pullup.
D1
RXDIN+
I
High-Speed Differential Receive Data Input.
E1
RXDIN–
Differential _{The receive clock and data signals RXCLK1,}
RXCLK2, and RXDOUT[15:0] are recovered
from the high-speed data signal present on
these pins.
Rev. 1.1
29