SI5100 Datasheet, PDF (26/40 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

Si5100
17. Pin Descriptions: Si5100
Alphabetically listed by name
Pin Number(s)
Name
I/O
M10
BWSEL1
I
M7
BWSEL0
F12
DLBK
I
K3
FIFOERR
O
M6
FIFORST
I
B1, C1–2, D2,
D5–11, E4, E11,
E2, F11, F1–2,
G11, G2, H11,
H2, J11, J1–4,
K11, K2, L5–11,
L2, M1–4
H12
GND
LLBK
GND
I
G3
LOS
O
C3
LOSLVL
I
Signal Level
LVTTL
LVTTL
LVTTL
LVTTL
Description
Transmit DSPLL Bandwidth Select.
The inputs select loop bandwidth of the Transmit
Clock Multiplier DSPLL as listed in Table 6.
Note: Both inputs have an internal pulldown.
Diagnostic Loopback.
When this input is low, the transmit clock and
data are looped back for output on RXDOUT,
RXCLK1 and RXCLK2. This pin should be held
high for normal operation.
Note: This input has an internal pullup.
FIFO Error.
This output is asserted (driven low) when a FIFO
overflow/underflow has occurred. This output is
low until reset by asserting FIFORST.
FIFO RESET.
When this input is low, the read/write FIFO point-
ers are reset to their initial state.
Note: This input has an internal pullup.
Supply Ground.
Connect to system GND. Ensure a very low
impedance path for optimal performance.
LVTTL
LVTTL
Line Loopback.
When this input is low, the recovered clock and
data are looped back for output on TXDOUT,
and TXCLKOUT. Set this pin high for normal
operation.
Note: This input has an internal pullup.
Loss-of-Signal.
This output is asserted (driven low) when the
peak-to-peak signal amplitude on RXDIN is
below the threshold set via LOSLVL.
LOS Threshold Level.
Applying an analog voltage to this pin allows
adjustment of the Threshold used to declare
LOS. Tieing this input to VREF disables LOS
detection and forces the LOS output high.
26
Rev. 1.1