SI5100 Datasheet, PDF (31/40 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

Pin Number(s)
D12
Name
RXMSBSEL
C11
RXREXT
C9
RXSQLCH
C4
SLICELVL
E12
SLICEMODE
N2
TXCLK16IN+
N1
TXCLK16IN–
Si5100
I/O Signal Level
Description
I
LVTTL Receive Data Bus Bit Order Select.
This determines the order of the received data
bits on the output bus.
When RXMSBSEL is set low, the first bit
received is output on RXDOUT0 and the follow-
ing bits are output in order on RXDOUT1
through RXDOUT15 (RXDOUT1 through
RXDOUT3 if MODE16 = 0). When RXMSBSEL
is set high, the first bit received is output on
RXDOUT15 (RXDOUT3) and the following bits
are output in order on RXDOUT14 (RXDOUT2)
through RXDOUT0.
Note: This input has an internal pulldown.
Receiver External Bias Resistor.
This resistor is used by the receiver circuitry to
establish bias currents within the device. This pin
must be connected to GND through a 3.09 kΩ
(1%) resistor.
I
LVTTL Receiver Data Squelch.
When this input is low the data on RXD-
OUT[15:0] is forced to a zero state. Set
RXSQLCH high for normal operation.
The RXSQLCH input is ignored when operating
in diagnostic loopback mode (DLBK = 0).
Note: This input has an internal pullup.
I
Slicing Level Adjustment.
Applying an analog voltage to this pin allows
adjustment of the slicing level applied to the
input data eye. Tying this input to VREF sets the
slicing offset to 0.
I
LVTTL Slice Level Adjustment Mode.
The SLICEMODE input is used to select the
mode of operation for slicing level adjustment.
When SLICEMODE = 0, absolute slice mode is
selected. When SLICEMODE = 1, proportional
slice mode is selected.
Note: This input has an internal pulldown.
I
LVDS
Differential Transmit Data Clock Input.
The rising edge of this input clocks data present
on TXDIN into the device. TXCLK 16IN is also
used as the Si5100 reference clock when the
REFSEL input is set low.
Rev. 1.1
31