S1011 Datasheet, PDF (9/43 Pages) Seiko Instruments Inc – BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_00
S-1011 Series
 Electrical Characteristics
1. VDD detection product
1. 1 S-1011 Series J / L type
Item
Symbol
Table 15
Condition
(Ta = +25°C unless otherwise specified)
Min.
Typ.
Max.
Unit
Test
Circuit
Detection voltage^*1
−V_DET
3.6 V ≤ −V_DET(S) ≤ 4.15 V
4.2 V ≤ −V_DET(S) ≤ 4.95 V
−V_DET(S)
× 0.970
−V_DET(S)
−V_DET(S)
× 1.030
V
1
−V_DET(S)
× 0.975
−V_DET(S)
−V_DET(S)
× 1.025
V
1
Hysteresis width
V_HYS
J type
L type^*2
3.6 V ≤ −V_DET(S) ≤ 4.15 V
−V_DET
−V_DET −V_DET
× 0.010 × 0.050 × 0.100
V
1
4.2 V ≤ −V_DET(S) ≤ 4.95 V
−V_DET
−V_DET −V_DET
× 0.020 × 0.050 × 0.090
V
1
3.6 V ≤ −V_DET(S) ≤ 4.95 V
−
0
−
V
1
Current consumption I_SS
Operation voltage
V_DD
V_DD = −V_DET − 0.1 V, 3.6 V ≤ −V_DET ≤ 4.95 V
−
−
0.60 1.60 μA 2
1.8
−
36.0 V
1
Output transistor
Output current
I_OUT
Nch
V_DD = 2.9 V
V_DS^*3 = 0.05 V
0.33
−
−
mA 3
Leakage current
I_LEAK
Output transistor
Nch
V_DD = 30.0 V, V_OUT = 30.0 V
−
Detection delay time^*4 t_RESET C_N = 3.3 nF
8.0
Release delay time^*5 t_DELAY C_P = 3.3 nF
8.0
−
2.0 μA 3
10.0 12.0 ms 4
10.0 12.0 ms 4
CP pin discharge
ON resistance
R_CP
V_DD = 6.9 V, V_CP = 0.5 V
0.52
−
2.2
kΩ
−
CN pin discharge
ON resistance
R_CN
V_DD = 2.9 V, V_CN = 0.5 V
1.0
−
5.0
kΩ
−
*1. −V_DET: Actual detection voltage value, −V_DET(S): Set detection voltage value
*2. Hysteresis width is "unavailable", so release voltage = detection voltage.
*3. V_DS: Drain-to-source voltage of the output transistor
*4. The time period from when the pulse voltage of −V_DET(S) + 0.5 V → −V_DET(S) − 0.5 V is applied to the VDD pin to when
V_OUT reaches V_DD / 2, after the power supply voltage (V_DD) reaches the release voltage once.
*5. The time period from when the pulse voltage of −V_DET(S) − 0.5 V → −V_DET(S) + 0.5 V is applied to the VDD pin to when
V_OUT reaches V_DD / 2.
Seiko Instruments Inc.
9