S1011 Datasheet, PDF (26/43 Pages) Seiko Instruments Inc – BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_00
4. Detection delay time accuracy (reference)
Figure 37 and Figure 38 show the relation between V_DD amplitude (V_P-P) and input voltage falling time (t_F) where
the arbitrarily set detection delay time accuracy can be maintained when the VDD pin (VDD detection product)
sharply drops.
S-1011A50
40.0
30.0
20.0
10.0
0.0
0.1
Ta = −40°C to +85°C
1
10
tF [s]
S-1011A50
40.0
30.0
20.0
10.0
0.0
0.1
Ta = −40°C to +85°C
1
10
tF [s]
Figure 37 C_N = 3.3 nF
Figure 38 C_N = 100 nF
tF
VIH^*1
VDET
VDD _VDET
VIL^*2
3.0 V
VSS
VP-P
*1. V_IH = 36.0 V
*2. V_IL = −V_DET(S) − 1.0 V (3.0 V min.)
Figure 39 VDD Pin Input Voltage Waveform
Caution
Figure 37 and Figure 38 show the input voltage conditions which can maintain the detection
delay time accuracy. If the voltage whose V_P-P and t_F are larger than these conditions is input to
the VDD pin (VDD detection product), the desired detection delay time may not be achieved.
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Seiko Instruments Inc.