S1011 Datasheet, PDF (25/43 Pages) Seiko Instruments Inc – BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_00
S-1011 Series
2. Power on and shut down sequence
SENSE detection products monitor SENSE pin voltage (V_SENSE) while power is being supplied to the VDD pin.
Apply power in the order, the VDD pin then the SENSE pin.
In addition, when shutting down VDD pin, shut down the SENSE pin first, and shut down the VDD pin after the
detection delay time (t_RESET) has elapsed.
VDD
VSENSE
VOUT
VDET
tDELAY
VDET(S)
tRESET
Figure 34
3. Falling power (reference)
Figure 35 shows the relation between V_DD amplitude (V_P-P) and input voltage falling time (t_F) where the release
status can be maintained when the VDD pin (VDD detection product) sharply drops to a voltage equal to or higher
than the detection voltage (−V_DET) during release status.
S-1011A50
40.0
Ta = −40°C to +85°C
30.0
20.0
10.0
0.0
0.1
1
10
tF [s]
Figure 35
tF
VIH^*1
VDET
VP-P
VDD VIL^*2
VDET
VSS
*1. V_IH = 36.0 V
*2. V_IL = −V_DET(S) + 1.0 V
Figure 36 VDD Pin Input Voltage Waveform
Caution
Figure 35 shows the input voltage conditions which can maintain the release status. If the
voltage whose V_P-P and t_F are larger than these conditions is input to the VDD pin (VDD detection
product), the OUT pin may change to a detection status.
Seiko Instruments Inc.
25