S1011 Datasheet, PDF (18/43 Pages) Seiko Instruments Inc – BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_00
1. 2 S-1011 Series C / L type
(1) When the power supply voltage (V_DD) is the release voltage (+V_DET) or higher, the Nch transistor is turned off to
output V_DD ("H") when the output is pulled up.
At this time, the input voltage to the comparator is
(R_B + R_C ) • V_DD
R_A + R_B + R_C
.
(2) When V_DD decreases to the detection voltage (−V_DET) or lower (point A in Figure 26), the Nch transistor is
turned on. And then V_SS ("L") is output from the OUT pin after the elapse of the detection delay time (t_RESET).
(3) The output is unstable when V_DD decreases to the IC's minimum operation voltage or lower. V_DD is output when
the output is pulled up.
(4) V_SS is output by increasing V_DD to the minimum operation voltage or higher.
(5) When V_DD increases to +V_DET or higher (point B in Figure 26), the Nch transistor is turned off. And then V_DD is
output from the OUT pin after the elapse of the release delay time (t_DELAY) when the output is pulled up.
VDD
V_DD
VSS
R_A
+
*1
−
R_B
V_REF
R_C
Delay
circuit
Nch
*1
*1
OUT
R
100 kΩ
*1
+
V
CP
CN
C_P
C_N
*1. Parasitic diode
Figure 25 Operation of S-1011 Series C / L Type
(1) (2) (3) (4) (5)
Detection voltage (−V_DET)
A
V_DD
Output from OUT pin
B
Release voltage (+V_DET)
Minimum operation voltage
V_SS
VDD
V_SS
Remark 1.
2.
t_RESET
t_DELAY
When V_DD is the minimum operation voltage or lower, the output voltage from the OUT pin is unstable
in the shaded area.
The release voltage is set to the same value as the detection voltage, since there is no hysteresis
width.
Figure 26 Timing Chart of S-1011 Series C / L Type
18
Seiko Instruments Inc.