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| S1011 Datasheet, PDF (17/43 Pages) Seiko Instruments Inc – BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR | |||
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HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_00
S-1011 Series
ï® Operation
1. Basic operation
1. 1 S-1011 Series A / J type
(1) When the power supply voltage (VDD) is the release voltage (+VDET) or higher, the Nch transistor is turned off to
output VDD ("H") when the output is pulled up.
Since the Nch transistor (N1) is turned off, the input voltage to the comparator is
(RB + RC ) ⢠VDD
RA + RB + RC
.
(2) Even if VDD decreases to +VDET or lower, VDD is output when VDD is higher than the detection voltage (âVDET).
When VDD decreases to âVDET or lower (point A in Figure 24), the Nch transistor is turned on. And then VSS ("L")
is output from the OUT pin after the elapse of the detection delay time (tRESET).
At this time, N1 is turned on, and the input voltage to the comparator is
RB ⢠VDD
RA + RB
.
(3) The output is unstable when VDD decreases to the IC's minimum operation voltage or lower. VDD is output when
the output is pulled up.
(4) VSS is output by increasing VDD to the minimum operation voltage or higher. Even if VDD exceeds âVDET, VSS is
output when VDD is lower than +VDET.
(5) When VDD increases to +VDET or higher (point B in Figure 24), the Nch transistor is turned off. And then VDD is
output from the OUT pin after the elapse of the release delay time (tDELAY) when the output is pulled up.
VDD
VDD
VSS
RA
*1
RB
VREF
RC
+
â
N1
Delay
circuit
Nch
*1
*1
OUT
R
100 kΩ
*1
+
V
CP
CN
CP
CN
*1. Parasitic diode
Figure 23 Operation of S-1011 Series A / J Type
(1) (2) (3) (4) (5)
Hysteresis width
(VHYS)
A
VDD
B
Release voltage (+VDET)
Detection voltage (âVDET)
Minimum operation voltage
VSS
VDD
Output from OUT pin
VSS
Remark
tRESET
tDELAY
When VDD is the minimum operation voltage or lower, the output voltage from the OUT pin is unstable in
the shaded area.
Figure 24 Timing Chart of S-1011 Series A / J Type
Seiko Instruments Inc.
17
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