S1011 Datasheet, PDF (10/43 Pages) Seiko Instruments Inc – BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_00
1. 2 S-1011 Series A / C type
Table 16
(Ta = +25°C unless otherwise specified)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Test
Circuit
Detection voltage^*1
−V_DET 5.0 V ≤ −V_DET(S) ≤ 10.0 V
−V_DET(S)
× 0.985
−V_DET(S)
−V_DET(S)
× 1.015
V
1
Hysteresis width
V_HYS
A type
C type^*2
−V_DET
−V_DET −V_DET
× 0.030 × 0.050 × 0.080
V
1
−
0
−
V
1
Current consumption I_SS
Operation voltage
V_DD
V_DD = −V_DET − 0.1 V, 5.0 V ≤ −V_DET ≤ 10.0 V
−
Output transistor
−
0.60 1.60 μA 2
1.8
−
36.0 V
1
Output current
I_OUT
Nch
V_DD = 4.5 V
V_DS^*3 = 0.05 V
0.5
−
−
mA 3
Leakage current
I_LEAK
Output transistor
Nch
V_DD = 30.0 V, V_OUT = 30.0 V
−
−
2.0 μA 3
Detection delay time^*4 t_RESET
Release delay time^*5 t_DELAY
C_N = 3.3 nF
C_P = 3.3 nF
8.0
10.0 12.0 ms 4
8.0
10.0 12.0 ms 4
CP pin discharge
ON resistance
R_CP
V_DD = 14.0 V, V_CP = 0.5 V
0.30
−
2.60 kΩ
−
CN pin discharge
ON resistance
R_CN
V_DD = 4.5 V, V_CN = 0.5 V
0.63
−
2.60 kΩ
−
*1. −V_DET: Actual detection voltage value, −V_DET(S): Set detection voltage value
*2. Hysteresis width is "unavailable", so release voltage = detection voltage.
*3. V_DS: Drain-to-source voltage of the output transistor
*4. The time period from when the pulse voltage of −V_DET(S) + 1.0 V → −V_DET(S) − 1.0 V is applied to the VDD pin to when
V_OUT reaches V_DD / 2, after the power supply voltage (V_DD) reaches the release voltage once.
*5. The time period from when the pulse voltage of −V_DET(S) − 1.0 V → −V_DET(S) + 1.0 V is applied to the VDD pin to when
V_OUT reaches V_DD / 2.
10
Seiko Instruments Inc.