S1011 Datasheet, PDF (19/43 Pages) Seiko Instruments Inc – BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_00
S-1011 Series
1. 3 S-1011 Series E / N type
(1) When the power supply voltage (V_DD) is the minimum operation voltage or higher, and the SENSE pin voltage
(V_SENSE) is the release voltage (+V_DET) or higher, the Nch transistor is turned off to output V_DD ("H") when the
output is pulled up.
Since the Nch transistor (N1) is turned off, the input voltage to the comparator is
(R_B +
R_A
R_C ) • V_SENSE
+ R_B + R_C
.
(2) Even if V_SENSE decreases to +V_DET or lower, V_DD is output when V_SENSE is higher than the detection voltage
(−V_DET).
When V_SENSE decreases to −V_DET or lower (point A in Figure 28), the Nch transistor is turned on. And then V_SS
("L") is output from the OUT pin after the elapse of the detection delay time (t_RESET).
At this time, N1 is turned on, and the input voltage to the comparator is
R_B •
R_A
V_SENSE
+ R_B
.
(3) Even if V_SENSE further decreases to the IC's minimum operation voltage or lower, the output from the OUT pin is
stable when V_DD is minimum operation voltage or higher.
(4) Even if V_SENSE exceeds −V_DET, V_SS is output when V_SENSE is lower than +V_DET.
(5) When V_SENSE increases to +V_DET or higher (point B in Figure 28), the Nch transistor is turned off. And then V_DD
is output from the OUT pin after the elapse of the release delay time (t_DELAY) when the output is pulled up.
VDD
V_DD
V_SENSE
VSS
SENSE
R_A
*1
*1
R_B
V_REF
R_C
+
−
N1
Delay
circuit
Nch
*1
*1
OUT
R
100 kΩ
*1
+
V
CP
CN
C_P
C_N
*1. Parasitic diode
Figure 27 Operation of S-1011 Series E / N Type
(1) (2) (3) (4) (5)
Hysteresis width
(V_HYS)
A
V_SENSE
B
Release voltage (+VDET)
Detection voltage (−V_DET)
Minimum operation voltage
V_SS
V_DD
Output from OUT pin
V_SS
t_RESET
t_DELAY
Figure 28 Timing Chart of S-1011 Series E / N Type
Seiko Instruments Inc.
19