S1011 Datasheet, PDF (27/43 Pages) Seiko Instruments Inc – BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_00
S-1011 Series
5. V_DD drop during release delay time (reference)
Figure 40 and Figure 41 show the relation between pulse width (t_PW) and V_DD lower limit (V_DROP) where a release
signal can be output after the normal release delay time has elapsed when the VDD pin (VDD detection product)
instantaneously drops to the detection voltage (−V_DET) or lower and then increases to the release voltage (+V_DET) or
higher during release delay time.
S-1011A50
Ta = −40°C to +85°C, C_P = C_N = 3.3 nF,
10000
1000
100
Inhibited Area
10
1
0.0
0.5
1.0
1.5
2.0
VDROP [V]
Figure 40
S-1011AA0
Ta = −40°C to +85°C, C_P = C_N = 3.3 nF,
10000
1000
100
Inhibited Area
10
1
0.0
0.5
1.0
1.5
2.0
VDROP [V]
Figure 41
16 V
tF^*1 tPW
tR^*1
VDD _VDET
VDROP
tDELAY  0.8
tDELAY
VOUT
*1. t_R = t_F = 10 μs
Figure 42 VDD Pin Input Voltage Waveform
Caution 1.
2.
Figure 40 and Figure 41 show the input voltage conditions when a release signal is output
after the normal release delay time has elapsed. When this is within the inhibited area, release
may erroneously be executed before the delay time completes.
When the VDD pin voltage is within the inhibited areas shown in Figure 40 and Figure 41
during release delay time, input 0 V to the VDD pin then restart the S-1011 Series.
Seiko Instruments Inc.
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