S1011 Datasheet, PDF (11/43 Pages) Seiko Instruments Inc – BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_00
S-1011 Series
2. SENSE detection product
2. 1 S-1011 Series N / Q type
Item
Symbol
Table 17
Condition
(Ta = +25°C unless otherwise specified)
Min.
Typ.
Max.
Unit
Test
Circuit
Detection voltage^*1
−V_DET
3.0 V ≤ −V_DET(S) ≤ 4.15 V
V_DD = 16.0 V
4.2 V ≤ −V_DET(S) ≤ 4.95 V
−V_DET(S)
× 0.970
−V_DET(S)
−V_DET(S)
× 1.030
V
1
−V_DET(S)
× 0.975
−V_DET(S)
−V_DET(S)
× 1.025
V
1
Hysteresis width
V_HYS
N type
V_DD = 16.0 V
3.0 V ≤ −V_DET(S) ≤ 4.15 V
4.2 V ≤ −V_DET(S) ≤ 4.95 V
−V_DET
× 0.010
−V_DET
× 0.020
−V_DET
× 0.050
−V_DET
× 0.050
−V_DET
× 0.100
−V_DET
× 0.090
V
V
1
1
Q type^*2 3.0 V ≤ −V_DET(S) ≤ 4.95 V
−
0
−
V
1
Current
consumption^*3
I_SS
Operation voltage
V_DD
Output current
I_OUT
Leakage current
I_LEAK
Detection delay time^*5 t_RESET
Release delay time^*6 t_DELAY
SENSE pin resistance R_SENSE
CP pin discharge
ON resistance
R_CP
CN pin discharge
ON resistance
R_CN
V_DD = 16.0 V, V_SENSE = −V_DET − 0.1 V,
3.0 V ≤ −V_DET ≤ 4.95 V
−
Output transistor
Nch
V_DS^*4 = 0.05 V
V_DD = 5.0 V, V_SENSE = 2.9 V
Output transistor V_DD = 30.0 V, V_OUT = 30.0 V,
Nch
V_SENSE = 30.0 V
C_N = 3.3 nF
C_P = 3.3 nF
−
V_DD = 3.0 V, V_SENSE = 6.9 V, V_CP = 0.5 V
V_DD = 3.0 V, V_SENSE = 2.9 V, V_CN = 0.5 V
−
3.0
0.5
−
8.0
8.0
6.8
0.72
0.72
0.55 1.55 μA 2
−
36.0 V
1
−
− mA 3
−
2.0 μA 3
10.0 12.0 ms 4
10.0 12.0 ms 4
−
275 MΩ 2
−
4.29 kΩ −
−
4.29 kΩ −
*1. −V_DET: Actual detection voltage value, −V_DET(S): Set detection voltage value
*2. Hysteresis width is "unavailable", so release voltage = detection voltage.
*3. The current flowing through the SENSE pin resistance is not included.
*4. V_DS: Drain-to-source voltage of the output transistor
*5. The time period from when the pulse voltage of −V_DET(S) + 0.5 V → −V_DET(S) − 0.5 V is applied to the SENSE pin to
when V_OUT reaches V_DD / 2, after voltage of 16.0 V is applied to the VDD pin and the SENSE pin input voltage (V_SENSE)
reaches the release voltage once.
*6. The time period from when voltage of 16.0 V is applied to the VDD pin and the pulse voltage of −V_DET(S) − 0.5 V →
−V_DET(S) + 0.5 V is applied to the SENSE pin to when V_OUT reaches V_DD / 2.
Seiko Instruments Inc.
11