SDA9206 Datasheet, PDF (53/54 Pages) Siemens Semiconductor Group – ADC with Built in Antialiasing filter and Clock generation UnitS

SDA 9206
5.3 Programmable Data Output Delay:
DAT_OUT: Pins PAQ7...0, PBQ7...0, BLN, HS, H1I1, H2I2 and VS
T
CLK1
DAT_OUT Data valid
t_QH
Data not valid
t _QD
Data valid
UET10469
Figure 23
DATDEL
000
001
t_QH; min.
6 ns
10 ns
t_QD; max.
25 ns
29 ns
The delay times are valid for a clock rate of the analog PLL of 27 MHz.
Semiconductor Group
53
1999-02-10