SDA9206 Datasheet, PDF (33/54 Pages) Siemens Semiconductor Group – ADC with Built in Antialiasing filter and Clock generation UnitS

SDA 9206
Subaddress 06_H
Bit
Name
D7
TV
D6
FREE
D5
VOFF
D4
VF
D3
TERM
Function
Selection of HPLL lock-in behavior:
0:
Optimum for VCR
1:
Optimum for SYNC from network
Generation of V pulse:
0:
V derived from SYNC
1:
Free-running generation; vertical frequency is
determined by VF bit, VOFF bit is enabled, SCHW bit
should be set to 1
Vertical noise suppression:
0:
Noise suppression enabled
1:
No noise suppression
Number of lines per field:
0:
312.5 or 312
1:
262.5 or 262
Note: VF must be set to the number of lines present in SYNC for
fly-wheel and noise suppression modes. VF determines
the number of lines per field for the free-running or
terminal mode.
Terminal mode:
FREE
TERM SCHW
VF Number of Lines
per Field generated
in Free-Running Mode
don’t care 1
don’t care 1
1
0
1
0
1
0
1
0
don’t care 0
don’t care 1
1
0
1
1
0
0
0
1
312
262
312.5
262.5
339
279
D2
GENMOD Clock generator mode
0:
Normal PLL mode
1:
Generator mode (fixed frequency output,
controlled by INC)
D1
0
Reserved
D0
SYPOL SYNC polarity:
0:
Negative sync signals (normal SYNC input)
1:
Positive sync signals
Semiconductor Group
33
1999-02-10