SDA9206 Datasheet, PDF (34/54 Pages) Siemens Semiconductor Group – ADC with Built in Antialiasing filter and Clock generation UnitS

SDA 9206
Subaddress 07_H
Bit
Name
D7
2FH
D6
HSWMA
D5
HSWMI
D4...D0 INC
Function
Selection of input frequency range:
0:
Normal line frequencies (around 15.6 kHz)
1:
Double line frequencies (31.2...38 kHz)
[YUV A/D converters are switched off]
Maximum width of HSYNC (input SYNC):
0:
6.2 µs for low FH-range
3.1 µs for high FH-range (2FH = 1)
1:
9.0 µs for low FH-range
4.5 µs for high FH-range (2FH = 1)
Minimum width of HSYNC (input SYNC):
0:
3.0 µs for low FH-range
1.5 µs for high FH-range (2FH = 1)
1:
1.7 µs for low FH-range
0.8 µs for high FH-range (2FH = 1)
Nominal PLL output frequency: INC = 00110
For the allowed values of INC refer to table chapter 2.3.1!
Calculation of INC for low FH range:
INC
=
INT_
f_--h-
f_q
*
110592 – 64,625_
for high FH range (2FH = 1):
INC
=
INT_
f_--h-
f_q
*
55292 – 64,625_
Semiconductor Group
34
1999-02-10