SDA9206 Datasheet, PDF (26/54 Pages) Siemens Semiconductor Group – ADC with Built in Antialiasing filter and Clock generation UnitS

SDA 9206
2.3.4 Miscellaneous Circuit Sections
To suppress bottom flutter in VCR mode, the frequency of the clock can be ’hold’ by
’freezing’ the increment of the HPLL. The vertical-frequency ’freezing-time’ starts a
number of lines (programmable by the I²C Bus) before the vertical pulse and then lasts
for a number (programmable) of lines. The settings do not depend on I²C-Bit TV. This
functionality is only available for the 1fh mode (2FH = 0).
VS
Line Number
of Half Picture
n-2 n-1 n
12345
Start 0...15 Lines before VS
15 14 13 12 3 2 1
Start
n = Number of Lines
in preceding Half Picture
0
Range over which
Frequency Value
is Frozen
Stop
0...15 Lines Duration
0 1 10 11 12 13 14 15
(In this example the frequency value was frozen 13 lines before the VS pulse and for
a duration of 11 lines.)
UED10466
Figure 17
I²C-Bus Programming Area which Clock Frequency Value Generated by HPLL
can be Frozen
An active low reset signal for other chips is available at pin RESOUTN. It is activated
when the chip supply voltage V_DD is switched on or when voltage glitches occur on it.
RESOUTN also is activated by pin RESIN. The RESOUTN pulse signal is not cancelled
until the crystal oscillator resonates and in addition stretched by an internal circuit for
approximately 127 lines (8 ms).
Semiconductor Group
26
1999-02-10