SDA9206 Datasheet, PDF (32/54 Pages) Siemens Semiconductor Group – ADC with Built in Antialiasing filter and Clock generation UnitS

SDA 9206
Subaddress 05_H
Bit
Name
D7
0
D6
SCHW
D5
HPLL
D4
VTHRE
D3
CLOF
D2...D0 000
Function
Reserved
Mode of vertical pulse generation:
0:
No flywheel mode
1:
Flywheel mode
Relationship between horizontal frequency in SYNC and default
frequency on CLK1 and CLK2:
0:
864
1:
858
Minimum sync pulse length from which a vertical pulse is
detected:
0:
26.6 µs
1:
11.3 µs
Clamping of SYNC for clock generator:
0:
Clamping on
1:
Clamping off
Reserved
Semiconductor Group
32
1999-02-10