SDA9206 Datasheet, PDF (18/54 Pages) Siemens Semiconductor Group – ADC with Built in Antialiasing filter and Clock generation UnitS

SDA 9206
The frequency response of the decimator filter stage 3 of the UV channels for an input
sampling rate of 6.75 MHz and an output sampling rate of 3.375 MHz is shown in
figure 13. The decimator stage 3 is active for 4:1:1 mode and can also be activated for
4:2:2 mode by I²C Bus (control bit UV3FIL).
UED10461
10
dB
0
-10
-20
-30
-40
-50
0
0.1
0.2
0.3
0.4
0.5
f / f_S
Figure 13
Frequency Response of the Chroma Decimator Stage 3
The Input Sampling Frequency f_S is 6.75 MHz
2.2 Data Output Formatter
Three output data formats can be selected via I²C Bus (control Bits FORMAT). One
format corresponds to CCIR 656 (8-Bit bus at a data rate of 27 MHz), an other format
makes available Y and UV data separately on 2 parallel 8-Bit buses for Y and UV at a
data rate of 13.5 MHz each. The third format is a 12-Bit bus with 8 connections for Y and
4 connections for multiplexed UV data.
Semiconductor Group
18
1999-02-10