SDA9206 Datasheet, PDF (48/54 Pages) Siemens Semiconductor Group – ADC with Built in Antialiasing filter and Clock generation UnitS

SDA 9206
3.2 Characteristics (Assuming Recommended Operating Conditions) (cont’d)
Parameter
Symbol
Limit Values Unit
min. nom. max.
Output data delay time, t_QD
referenced to CLK1
(not valid for ESOUTN)
25 ns
Remark
DATDEL = 000
C_L = 15 pF
5 V output stage
supply voltage,
DATSLOP = 0
35 ns DATDEL = 000
C_L = 25 pF
5 V output stage
supply voltage,
DATSLOP = 0
Output data hold time, t_QH
6
referenced to CLK1
(not valid for
RESOUTN)
Pin RESOUTN
Data delay/
data hold time
-
-
Clock TTL Outputs CLK1, CLK2
L-output voltage
H-output voltage
Load capacitance
Transition times
V_QL
V_QH
C_L
t_R, t_F
0
2.4 V
25 ns DATDEL = 000
C_L = 25 pF
3.3 V output stage
supply voltage,
FORMAT = 00
DATSLOP = 1
ns
-
Asynchronous output
signal
0.4 V
V_DD 1
30 pF
5
ns
I = 1 mA
I = - 0.5 mA
5 V output stage
supply voltage,
CLKSLOP = 00
3.3 V output stage
supply voltage,
CLKSLOP = 10
Semiconductor Group
48
1999-02-10