SDA9206 Datasheet, PDF (16/54 Pages) Siemens Semiconductor Group – ADC with Built in Antialiasing filter and Clock generation UnitS

SDA 9206
2.1.3 Clamping
The analog pins AINY, AINU, AINV are switched simultaneously to on chip generated
clamping levels by an on chip clamping pulse H2.
Analog Channel
AINY
AINU, AINV
Straight Binary
Code
0001 0000
1000 0000
Two’s Complement
Code
1001 0000
0000 0000
Components
Y
U, V
The external clamping capacitance is loaded by on chip current sources during
clamping. So loading time depends on the values of C_{ext cl} .
2.1.4 Digital Decimation Filters for YUV
The data rates of digital YUV signals are reduced in decimation filters following the
A/D conversion. The overall performance of the decimation filters is tuned to the
requirements for TV signals.
In figure 11 the frequency response of the filter for the Y channel is shown. The input
sampling rate is 27 MHz, the output sampling rate is 13.5 MHz.
10
UED10459
dB
0
-10
-20
-30
-40
-50
0
0.1
0.2
0.3
0.4
0.5
f / f_S
Figure 11
Magnitude Frequency Response of the Luminance Filter
The Input Sampling Frequency f_S is 27 MHz
Semiconductor Group
16
1999-02-10