SDA9206 Datasheet, PDF (22/54 Pages) Siemens Semiconductor Group – ADC with Built in Antialiasing filter and Clock generation UnitS

SDA 9206
to adapt the nominal frequency of the DTO by means of 5 I²C-Bus bits (INC4...INC0)
such shifting the center frequency according to the momentary standard used.
For the different applications the following values of INC are allowed (values valid for
a crystal frequency of 24.576 MHz):
Application
FH [Hz]
2FH
PAL
15625
0
NTSC
15750
0
PAL (100 Hz/VGA) 31250
1
NTSC (120 Hz/VGA) 31500
1
ATV
32400
1
MUSE
33750
1
Macintosh
35000
1
VGA
38000
1
YUV-ADCs INC
active
6
active
6
inactive
6
inactive
6
inactive
8
inactive
11
inactive
14
inactive
21
Note: A change of INC causes spontaneous changes of the generated clock
frequencies!
The DTO generates a saw-tooth with a frequency that is proportional to the increment.
The saw-tooth is converted into a sinusoidal clock signal by means of a D/A converter
and applied to an analog PLL which multiplies the frequency and minimizes residual
jitter.
By means of the I²C bits S1CL and S2CL the output frequency on pins CLK1 and CLK2
can be set. In this manner a clock is provided that is line-locked with the SYNC-input
signal. The ratio of these clock frequencies to the horizontal frequency of SYNC depends
only on the I²C-Bus bits S1CL, S2CL, HPLL and 2FH.
For the different modes the following values of S1CL and S2CL are allowed:
Mode
YUV-ADC 2FH
CCIR
enabled 0
CCIR
enabled 0
4:2:2, 4:1:1 enabled 0
4:2:2, 4:1:1 enabled 0
VGA
disabled 1
VGA
disabled 1
S1CL
11
11
11
10
01
10
S2CL
11
00
11
00
11
11
f_CLK1
(MHz)
f_CLK2
(MHz)
27
27
27
tristate
27
27
13.5
tristate
6.25 ... 8.75 25 ... 35
12.5 ... 17.5 25 ... 35
The digital horizontal PLL supplies a noise-suppressed horizontal pulse.
Semiconductor Group
22
1999-02-10