SDA9206 Datasheet, PDF (15/54 Pages) Siemens Semiconductor Group – ADC with Built in Antialiasing filter and Clock generation UnitS

SDA 9206
2
System Description
2.1 A/D Converter for YUV Inputs
2.1.1 Introduction
The SDA 9206 implements 3 independent 8-Bit A/D converters.
Maximum conversion rate is 30 MHz.
2.1.2 Input Signal Amplification, Prefiltering
The amplification of the input signals can be adjusted via I²C Bus. An internal prefiltering
of the analog input signals is implemented. The typ. frequency response of the analog
antialiasing prefilter is shown in figure 10.
0
dB
-10
-20
-30
-40
-50
-60
-70
10
0
5
10 ¹
UED10458
5 MHz 10 ²
Frequency
Figure 10
Frequency Response of the Analog Antialiasing Prefilter
Semiconductor Group
15
1999-02-10