GV7704 Datasheet, PDF (6/52 Pages) Semtech Corporation – Quad HD-VLC Receiver

1.2 Pin Descriptions
Table 1-1: GV7704 Pin Descriptions
Pin Number
Name
Type
Description
Analog High-Speed Inputs
N1, N2
CH0_SDI, CH0_SDI
K1, K2
CH1_SDI, CH1_SDI
D1, D2
CH2_SDI, CH2_SDI
A1, A2
CH3_SDI, CH3_SDI
Analog High-Speed Outputs
N4, M4
CH0_SDO, CH0_SDO
H1, H2
CH1_SDO, CH1_SDO
F1, F2
CH2_SDO, CH2_SDO
A4, B4
CH3_SDO, CH3_SDO
Analog Bias
L1
RBIAS
Digital Video Outputs
L8, L9, L10, M8,
M9, M10, M11,
N8, N9, N10
CH0_DOUT_[9:0]
Analog
High-Speed
Input
Analog
High-Speed
Input
Analog
High-Speed
Input
Analog
High-Speed
Input
Differential high-speed data input 0.
(75Ω nominal input impedance)
Differential high-speed data input 1.
(75Ω nominal input impedance)
Differential high-speed data input 2.
(75Ω nominal input impedance)
Differential high-speed data input 3.
(75Ω nominal input impedance)
Analog
High-Speed
Output
Analog
High-Speed
Output
Analog
High-Speed
Output
Analog
High-Speed
Output
Differential high-speed test output 0.
(75Ω nominal output impedance)
Differential high-speed test output 1.
(75Ω nominal output impedance)
Differential high-speed test output 2.
(75Ω nominal output impedance)
Differential high-speed test output 3.
(75Ω nominal output impedance)
Input/Output
External 10kΩ resistor for bias reference. Connect the resistor to
ground.
Output
Parallel digital video output.
High impedance when signal is not present or user disables the
lane (DISABLE_VIDEO_LANE).
Drive strength may be adjusted using register
PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG.
GV7704
Preliminary Data Sheet Rev.3
PDS-060376
September 2015
www.semtech.com
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