GV7704 Datasheet, PDF (28/52 Pages) Semtech Corporation – Quad HD-VLC Receiver

4.8 Audio Extraction
The GV7704 will de-embed audio from both HD and HD-VLC encoded data. The GV7704
can extract up to four channels of serial digital audio at an audio sampling rate of 32kHz,
44.1kHz, or 48kHz. By default, audio extraction for each channel is enabled, and it can be
disabled on any channel by setting DISABLE_AUDIO to 01 in the
AUDIO_CTRL_OVERRRIDE_REG register from the host interface.
By default, the device will process audio at a sampling rate of 48kHz. When using a
GV7700 to GV7704 chip set, audio sampled at 44.1kHz and 32kHz will be automatically
detected by the GV7704. The GV7704 reads the Stream ID packet byte 3 to determine
the audio sampling frequency.
When receiving from a signal not transmitted by the GV7700, the audio sampling rate
must be manually specified if different than 48kHz, first by setting
AUDIO_SAMP_FREQ_MANUAL_MODE to 1, and then by specifying the sampling
frequency through AUDIO_SAMP_FREQ. Refer to Table 4-9 below.
Table 4-9: Register Settings for Manual Audio Sampling Frequency
AUDIO_SAMP_FREQ
00 (default)
01
10
11
Sampling Frequency
48khz
44.1kHz
32kHz
Reserved
The device will continuously look for the programmable audio group DID and updates
the audio packets present on every rising edge of the vertical blanking interval. If several
audio groups are present in the video signal, the device will extract the lower Audio
Group number (ex: Audio Group 2, Audio Group 8: Audio Group 2 will be extracted). As
such, the programmable audio group DID is offered to the user as a method of selecting
the audio group of his choice for extraction or for specifying an audio DID that would be
different from the 8 HD audio group DIDs specified in the SMPTE standards.
The audio packet format is SMPTE ST 299-1, regardless of the input signal rate (270Mb/s
or 1.485Gb/s). The GV7704 will compute ECC (Error Correcting Codes) and compare
them to the ECC embedded in the audio packets, and it will correct errors wherever
possible as well as report any errors found. Error correction can be disabled by setting
DISABLE_ECC to 01 in the AUD_EXT_CONFIG_REG register, and the audio samples will
be bypassed as found in the packets.
The audio samples will be buffered and output on the four I²S channels via CHn_ACLK,
CHn_WCLK, CHn_AIN_1_2, and CHn_AIN_3_4 pins. They will be formatted according to
the standard I²S bus specifications, and the timing for this interface is shown in
Figure 4-11 below.
GV7704
Preliminary Data Sheet Rev.3
PDS-060376
September 2015
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