GV7704 Datasheet, PDF (33/52 Pages) Semtech Corporation – Quad HD-VLC Receiver

4.9.7 GSPI Transaction Timing
t₀
t₁
t₂
t₄
t₇
SCLK
CS
SDIN
SDOUT
t₃
t₈
R/W 0
1
Auto_
Inc
0
0
0
0
0 A14 A13
R/W 0
1
Auto_
Inc
0
0
0
0
0 A14 A13
32 SCLK cycles
A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDIN signal is looped out on SDOUT
16 SCLK cycles
Write Mode
High-Z
t₅
SCLK
CS
SDIN
SDOUT
R/W 0
R/W 0
1
Auto_
Inc
0
0
0
0
0 A14 A13
1
Auto_
Inc
0
0
0
0
0 A14 A13
32 SCLK cycles
SDIN signal is looped out on SDOUT
A3 A2 A1 A0
A3 A2 A1 A0
Read Mode
SCLK
CS
SDIN
SDOUT
COMMAND
COMMAND
Figure 4-14: GSPI External Interface Timing
t₉
t₆
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
16 SCLK cycles
Read Data is output on SDOUT
High-Z
t_cmd
t₉
DATA
DATA
X
High-Z
COMMAND
COMMAND
Table 4-12: GSPI Timing Parameters
Parameter
Symbol
Min
Typ
Max
Units
CS LOW before SCLK rising edge
t₀
2.0
—
SCLK frequency
—
—
SCLK period
t₁
18.2
—
SCLK duty cycle
t₂
40
50
Input data setup time
t₃
2.7
—
SCLK idle time — write
t₄
41.7
—
SCLK idle time — read
t₅
162
—
Inter-command delay time
t_cmd
162
—
SDOUT after SCLK falling edge
t₆
—
—
CS HIGH after final SCLK falling
edge
t₇
0.0
—
Input data hold time
t₈
1.0
—
—
ns
55
MHz
—
ns
60
%
—
ns
—
ns
—
ns
—
ns
7.5
ns
—
ns
—
ns
GV7704
Preliminary Data Sheet Rev.3
PDS-060376
September 2015
www.semtech.com
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Semtech