GV7704 Datasheet, PDF (24/52 Pages) Semtech Corporation – Quad HD-VLC Receiver

from the second TRS, line number and line CRC with blanking values, as shown in
Figure 4-7. Note that when BT.656 output mode is enabled, any embedded ancillary
data in the horizontal balking will remain unchanged, and will not be contiguous from
the EAV. This is shown in Figure 4-8 below.
CHn_PCLK
CHn_DOUT_[9:0]
CHn_HOUT
CHn_VOUT
CHn_FOUT
Cb, n-4 Y, n-4 Cr, n-4 Y, n-3 Cb, n-2 Y, n-2 Cr, n-2 Y, n-1 3FFh 000h 000h EAV 200h 040h 200h 040h 200h 040h 200h 040h 200h 040h 200h 040h 200h 040h 200h 040h 200h
Inserted Blanking Words
CHn_DOUT_[9:0]
CHn_HOUT
200h 040h 200h 040h 200h 040h 3FFh 000h 000h SAV Cb, 0 Y, 0 Cr, 0 Y, 1 Cb, 2 Y, 2 Cr, 2 Y, 3 Cb, 4 Y, 4 Cr, 4 Y, 5 Cb, 6 Y, 6 Cr, 6 Y, 7 Cb, 8 Y, 8 Cr, 8 Y, 9 Cb, 10
Inserted Blanking Words
Figure 4-7: BT.656 Video Output Timing
CHn_DOUT_[9:0] 3FFh 000h 000h EAV 200h 040h 200h 040h 200h 040h 200h 040h 200h 040h 200h 040h 000h 040h 3FFh 040h 3FFh 040h
Inserted Blanking Words
Ancillary Data
Figure 4-8: Ancillary Data in BT.656 Video Output Timing Mode
4.5 Parallel Video Data Outputs CHn_DOUT_[9:0]
A 10-bit video output bus is provided for each received video channel. The parallel data
outputs are aligned to the rising edge of PCLK. Each output provides a 10-bit
multiplexed ITU-R BT.1120 compliant video bus with embedded TRS. The drive strength
of the parallel video output pins (PCLK, HOUT, VOUT, FOUT, DOUT[9:0]) can be adjusted
using the PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL bit. The device uses the low
drive strength setting by default. For PCB trace longer than 6 inches the high drive
strength setting should be used.
CHn_PCLK
CHn_DOUT[9:0],
CHn_FOUT,
CHn_HOUT,
CHn_VOUT
data_* is launched on the positive edge of PCLK
PCLK period
t_OD
data_0
transition zone
data_0 _{data_0}
transition zone
t_H
t_OD
data_1
transition zone
Figure 4-9: GV7704 Parallel Video Output Timing Diagram
t_SU
t_H
data_1
GV7704
Preliminary Data Sheet Rev.3
PDS-060376
September 2015
www.semtech.com
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Semtech