GV7704 Datasheet, PDF (35/52 Pages) Semtech Corporation – Quad HD-VLC Receiver

In this mode, multiple Data Words can be read from/written to the device using only one
starting address. Each access is initiated by a HIGH-to-LOW transition of the CS pin, and
consists of a Command Word and one or more Data Words. The internal address is
automatically incremented after the first read or write Data Word, and continues to
increment until the read or write access is terminated by a LOW-to-HIGH transition of
the CS pin.
Note: Writing to HOST_CONFIG using Auto-increment access is not allowed.
The maximum interface clock frequency (SCLK) is 55MHz and the inter-command delay
time indicated in the diagram as t_cmd, is a minimum of 162ns.
For read access, the time from the last bit of the first Command Word to the start of the
data output of the first Data Word as defined by t₅, will be no less than 162ns. All
subsequent read data accesses will not be subject to this delay during an
Auto-Increment read.
SCLK
CS
SDIN
SDOUT
COMMAND [31:16]
COMMAND [31:16]
COMMAND [15:0]
COMMAND [15:0]
Figure 4-17: GSPI Write Timing – Auto-Increment
DATA 1
DATA 1
DATA 2
DATA 2
SCLK
CS
SDIN
COMMAND [31:16]
t
5
COMMAND [15:0]
SDOUT
COMMAND [31:16]
COMMAND [15:0]
Figure 4-18: GSPI Read Timing – Auto-Increment
DATA 1
DATA 2
4.10 JTAG
The GV7704 provides an IEEE 1149.1-compliant JTAG TAP interface for boundary scan
test and debug.
The GV7704 TAP interface consists of the TCK clock input, TRST, TDI and TMS inputs, and
the TDO output as defined in the standard. TMS and TDI inputs are clocked with respect
to the rising edge of TCK and the TDO output with respect to the falling edge of TCK.
GV7704
Preliminary Data Sheet Rev.3
PDS-060376
September 2015
www.semtech.com
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Semtech