GV7704 Datasheet, PDF (30/52 Pages) Semtech Corporation – Quad HD-VLC Receiver

Table 4-11: Audio Mute Controls
Address
Channel 0: 488D_h
Channel 1: 548D_h
Channel 2: 608D_h
Channel 3: 6C8D_h
Register
AUD_EXT_CONFIG_
REG
Parameter
MUTE_0_1
MUTE_2_3
Description
HIGH = Channels 0 & 1 are muted
LOW = Channels 0 & 1 are not muted
HIGH = Channels 2 & 3 are muted
LOW = Channels 2 & 3 are not muted
4.9 GSPI Host Interface
The GV7704 is controlled via the Gennum Serial Peripheral Interface (GSPI).
The GSPI host interface is comprised of a serial data input signal (SDIN pin), serial data
output signal (SDOUT pin), an active-low chip select (CS pin) and a burst clock (SCLK
pin).
The GV7704 is a slave device, so the SCLK, SDIN and CS signals must be sourced by the
application host processor.
All read and write access to the device is initiated and terminated by the application
host processor.
4.9.1 CS Pin
The Chip Select pin (CS) is an active-low signal provided by the host processor to the
GV7704.
The HIGH-to-LOW transition of this pin marks the start of serial communication to the
GV7704.
The LOW-to-HIGH transition of this pin marks the end of serial communication to the
GV7704.
4.9.2 SDIN Pin
The SDIN pin is the GSPI serial data input pin of the GV7704.
The 16-bit Command and Data Words from the host processor are shifted into the
device on the rising edge of SCLK when the CS pin is LOW.
4.9.3 SDOUT Pin
The SDOUT pin is the GSPI serial data output of the GV7704.
All data transfers out of the GV7704 to the host processor occur from this pin.
By default at power up or after system reset, the SDOUT pin provides a non-clocked path
directly from the SDIN pin, only when the CS pin is LOW, except during the GSPI Data
Word portion for read operations to the device. When the CS pin is HIGH, the SDOUT pin
will be in a high-impedance state.
GV7704
Preliminary Data Sheet Rev.3
PDS-060376
September 2015
www.semtech.com
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