GV7704 Datasheet, PDF (37/52 Pages) Semtech Corporation – Quad HD-VLC Receiver

5. Register Map
Table 5-1: GV7704 Register Descriptions — Channel Controls
Address
Register Name
Parameter Name
Bit
Slice
4078_h
GSPI_SDOUT_DRV_
STRENGTH_SEL_REG
GSPI_SDOUT_DRV_
STRENGTH_SEL
0:0
44F1_h (Ch 0)
50F1_h (Ch 1)
5CF1_h (Ch 2)
INPUT_TERMINATION_
REG
INPUT_TERMINATION
0:0
68F1_h (Ch 3)
44F2_h (Ch 0)
PU_DRVN
0:0
50F2_h (Ch 1)
POWER_UP_DRIVER_REG
5CF2_h (Ch 2)
68F2_h (Ch 3)
PU_DRVP
1:1
44F3_h (Ch 0)
50F3_h (Ch 1)
P2S_CLK_EN_REG
P2S_CLK_EN
0:0
5CF3_h (Ch 2)
68F3_h (Ch 3)
44F4_h (Ch 0)
50F4_h (Ch 1)
5CF4_h (Ch 2)
68F4_h (Ch 3)
P2S_RSTB_REG
P2S_RSTB
0:0
44F5_h (Ch 0)
50F5_h (Ch 1)
CDR_TX_CLK_EN_REG CDR_TX_CLK_EN
0:0
5CF5_h (Ch 2)
68F5_h (Ch 3)
44F6_h (Ch 0)
50F6_h (Ch 1)
5CF6_h (Ch 2)
68F6_h (Ch 3)
SDO_50_EN_REG
SDO_50_EN
0:0
R/W
Reset
Value
Description
GSPI SDOUT drive strength select.
RW
1_b 1_b = high drive strength
0_b = low drive strength
Sets the receive input termination
impedance.
RW
1_b Termination is to VDD18.
0_b = 50Ω
1_b = 75Ω
Power up control for the SDO_N
path
RW
0_b
0_b = Power down
1_b = Power up
Power up control for the SDO_P
path
RW
0_b
0_b = Power down
1_b = Power up
Parallel to serial converter in
transmit path clock buffer enable
RW
0_b 0_b = Clocks in the p2s are turned
off
1_b = Clocks in the p2s are enabled
Parallel to serial converter in
transmit path reset
RW
0_b
0_b = Hold p2s flops in reset
1_b = P2s not in reset
Enable for transmit path clock
0_b = Turn off half rate clock to the
RW
0_{b p2s in the transmit path}
1_b = Turn on half rate clock to the
p2s in the transmit path
SDO_P/N 50Ω termination enable
RW
0_b 0_b = 75Ω termination
1_b = 50Ω termination
GV7704
Preliminary Data Sheet Rev.3
PDS-060376
September 2015
www.semtech.com
37 of 52
Semtech