K4S161622D Datasheet, PDF (6/41 Pages) Samsung semiconductor – 512K x 16Bit x 2 Banks Synchronous DRAM

K4S161622D
Parameter
Symbol
CLK cycle time
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
tCC(min)
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
-55
5.5
11
16.5
16.5
38.5
55
Version
-60
-70
-80
6
7
8
12
14
16
18
17.4
20
18
17.4
20
42
43.5
48
100
60
60.9
70
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. Also, supported tRDL=2CLK for - 55/60 part which is distinguished by bucket code "J".
From the next generation, tRDL will be only 2CLK for every clock frequency.
CMOS SDRAM
Unit
-10
10
ns
20
ns
20
ns
20
ns
48
ns
us
70
ns
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
CLK cycle time
CAS Latency=3
CAS Latency=2
CLK to valid
output delay
CAS Latency=3
CAS Latency=2
Output data
CAS Latency=3
CLK high pulse width
CAS Latency=2
CLK low pulse width
CAS Latency=3
CAS Latency=2
Input setup time
CAS Latency=3
CAS Latency=2
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
CAS Latency=3
CAS Latency=2
-55
Symbol
-60
-70
-80
-10
Unit Note
Min Max Min Max Min Max Min Max Min Max
5.5
6
7
8
10
tCC
1000
1000
1000
1000
1000 ns 1
-
-
8.7
10
12
-
5
- 5.5 - 5.5 - 6
-
6
tSAC
ns 1, 2
-
-
-
-
- 7.7 - 6
-8
tOH
2
- 2.5 - 2.5 - 2.5 - 2.5 - ns 2
2
2.5
tCH
-
-
3
-
3
- 3.5 -
ns 3
-
-
2
2.5
tCL
-
-
3
-
3
- 3.5 -
ns 3
-
1.5
1.5
1.75
tSS
-
-
- 2 - 2.5 - ns 3
-
-
2.5
tSH
1
-
1
-
1
-
1
-
1
- ns 3
tSLZ
1
-
1
-
1
-
1
-
1
- ns 2
-
5
- 5.5 - 5.5 - 6
-
6
tSHZ
ns
-
-
-
-
- 7.7 -
6
-
8
Note : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.