K4S161622D Datasheet, PDF (2/41 Pages) Samsung semiconductor – 512K x 16Bit x 2 Banks Synchronous DRAM

K4S161622D
CMOS SDRAM
PIN CONFIGURATION (TOP VIEW)
VDD 1
DQ0 2
DQ1 3
VSSQ 4
DQ2 5
DQ3 6
VDDQ 7
DQ4 8
DQ5 9
VSSQ 10
DQ6 11
DQ7 12
VDDQ 13
LDQM 14
WE 15
CAS 16
RAS 17
CS 18
BA 19
A10/AP 20
A0 21
A1 22
A2 23
A3 24
VDD 25
PIN FUNCTION DESCRIPTION
50 VSS
49 DQ15
48 DQ14
47 VSSQ
46 DQ13
45 DQ12
44 VDDQ
43 DQ11
42 DQ10
41 VSSQ
40 DQ9
39 DQ8
38 VDDQ
37 N.C/RFU
36 UDQM
35 CLK
34 CKE
33 N.C
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 VSS
50PIN TSOP (II)
(400mil x 825mil)
(0.8 mm PIN PITCH)
Pin
CLK
CS
Name
System Clock
Chip Select
CKE
Clock Enable
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A0 ~ A10/AP Address
BA
Bank Select Address
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
L(U)DQM Data Input/Output Mask
DQ0 ~ 15
VDD/VSS
Data Input/Output
Power Supply/Ground
VDDQ/VSSQ Data Output Power/Ground
N.C/RFU
No Connection/
Reserved for Future Use
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.