K4S161622D Datasheet, PDF (4/41 Pages) Samsung semiconductor – 512K x 16Bit x 2 Banks Synchronous DRAM

K4S161622D
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Symbol
Test Condition
CAS
Latency _-55
Version
-60 -70 -80
Unit Note
-10
Operating Current
(One Bank Active)
ICC1
Burst Length =1
tRC≥tRC(min)
Io = 0 mA
3
120 115 105 95 85
mA 2
2
-
- 110 95 80
Precharge Standby Cur-
rent in power-down mode
ICC2P
ICC2PS
CKE≤VIL(max), tCC = 15ns
CKE & CLK≤VIL(max), tCC = ∞
2
mA
2
Precharge Standby Current
in non power-down mode
ICC2N
ICC2NS
CKE≥VIH(min), CS≥VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
CKE≥VIH(min), CLK≤VIL(max), tCC = ∞
Input signals are stable
15
mA
5
Active Standby Current
in power-down mode
ICC3P
ICC3PS
CKE≤VIL(max), tCC = 15ns
CKE & CLK≤VIL(max), tCC = ∞
3
mA
3
Active Standby Current
in non power-down mode
(One Bank Active)
ICC3N
CKE≥VIH(min), CS≥VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
ICC3NS
CKE≥VIH(min), CLK≤VIL(max), tCC = ∞
Input signals are stable
25
mA
15
mA
Operating Current
(Burst Mode)
Io = 0 mA
3
155 150 140 130 115
ICC4
Page Burst 2Banks Activated
mA 2
tCCD = 2CLKs
2
-
- 125 115 100
Refresh Current
ICC5
Self Refresh Current
ICC6
tRC≥tRC(min)
CKE≤0.2V
3
105 100 90 90 80
mA 3
2
-
- 100 90 80
1
mA 4
250
uA 5
Note : _{1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.}
2. Measured with outputs open. Addresses are changed only one time during tcc(min).
3. Refresh period is 32ms. Addresses are changed only one time during tcc(min).
4. K4S161622D-TC**
5. K4S161622D-TL**