K4S161622D Datasheet, PDF (29/41 Pages) Samsung semiconductor – 512K x 16Bit x 2 Banks Synchronous DRAM

K4S161622D
Page Read Cycle at Different Bank @Burst Length=4
CMOS SDRAM
CLOCK
CKE
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
*Note 1
HIGH
RAS
CAS
*Note 2
ADDR
RAa
CAa RBb
CBb
CAc
CBd
CAe
BA
A10/AP
RAa
RBb
DQ CL=2
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
CL=3
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
WE
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
Read
(A-Bank)
Read
(B-Bank)
Read
(A-Bank)
Read
Read
(B-Bank) (A-Bank)
Precharge
(A-Bank)
: Don't care
*Note : 1. CS can be don't cared when RAS, CAS and WE are high at the clock high going dege.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.