K4S161622D Datasheet, PDF (14/41 Pages) Samsung semiconductor – 512K x 16Bit x 2 Banks Synchronous DRAM

K4S161622D
3. CAS Interrupt (I)
Note 1
1) Read interrupted by Read (BL=4)
CLK
CMD
ADD
DQ(CL2)
DQ(CL3)
RD RD
AB
tCCD
Note 2
QA0 QB0 QB1 QB2 QB3
QA0 QB0 QB1 QB2 QB3
CMOS SDRAM
2) Write interrupted by Write (BL=2)
CLK
CMD
ADD
WR WR
tCCD Note 2
AB
DQ
DA0 DB0 DB1
tCDL
Note 3
3) Write interrupted by Read (BL=2)
DQ(CL2)
DQ(CL3)
WR RD
tCCD Note 2
AB
DA0
DA0
tCDL
Note 3
QB0 QB1
QB0 QB1
*Note : 1. By " Interrupt", It is meant to stop burst read/write by external command before the end of burst.
By "CAS Interrupt", to stop burst read/write by CAS access ; read and write.
2. tCCD : CAS to CAS delay. (=1CLK)
3. tCDL : Last data in to new column address delay. (=1CLK)