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K4S161622D Datasheet, PDF (1/41 Pages) Samsung semiconductor – 512K x 16Bit x 2 Banks Synchronous DRAM
K4S161622D
512K x 16Bit x 2 Banks Synchronous DRAM
CMOS SDRAM
FEATURES
• 3.3V power supply
• LVTTL compatible with multiplexed address
• Dual banks operation
• MRS cycle with address key programs
-. CAS Latency ( 2 & 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock
• Burst Read Single-bit Write operation
• DQM for masking
• Auto & self refresh
• 15.6us refresh duty cycle (2K/32ms)
GENERAL DESCRIPTION
The K4S161622D is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,
fabricated with SAMSUNG′s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
ORDERING INFORMATION
Part NO.
K4S161622D-TC/L55
K4S161622D-TC/L60
K4S161622D-TC/L70
K4S161622D-TC/L80
K4S161622D-TC/L10
MAX Freq.
183MHz
166MHz
143MHz
125MHz
100MHz
Interface Package
LVTTL
50
TSOP(II)
FUNCTIONAL BLOCK DIAGRAM
Bank Select
Data Input Register
LWE
LDQM
512K x 16
CLK
ADD
512K x 16
Column Decoder
LCKE
LRAS LCBR
LWE
LCAS
Latency & Burst Length
Programming Register
LWCBR
Timing Register
DQi
LDQM
CLK
CKE
CS
RAS
CAS
WE L(U)DQM
* Samsung Electronics reserves the right to
change products or specification without
notice.