K4S161622D Datasheet, PDF (17/41 Pages) Samsung semiconductor – 512K x 16Bit x 2 Banks Synchronous DRAM

K4S161622D
6. Precharge
1) Normal Write (BL=4)
CLK
CMD
WR
PRE
DQ
D0 D1 D2 D3
tRDL
Note 2
2) Normal Read (BL=4)
CLK
CMD
RD
DQ(CL2)
DQ(CL3)
PRE
1
Q0 Q1 Q2 Q3
Note 2
2
Q0 Q1 Q2 Q3
CMOS SDRAM
7. Auto Precharge
1) Normal Write (BL=4)
CLK
CMD
WR
DQ
D0 D1 D2 D3
2) Normal Read (BL=4)
Note 3
Auto Precharge Starts
CLK
CMD
RD
DQ(CL2)
DQ(CL3)
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Note 3
Auto Precharge Starts
*Note : 1. tRDL : Last data in to row precharge delay
2. Number of valid output data after row precharge : 0, 1, 2 for CAS Latency =1, 2, 3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of the other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/other bank is illegal.