K4S161622D Datasheet, PDF (31/41 Pages) Samsung semiconductor – 512K x 16Bit x 2 Banks Synchronous DRAM

K4S161622D
Read & Write Cycle at Different Bank @Burst Length=4
CMOS SDRAM
CLOCK
CKE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
HIGH
CS
RAS
CAS
ADDR
RAa
CAa
RBb
CBb RAc
CAc
BA
A10/AP
RAa
DQ CL=2
RBb
QAa0 QAa1 QAa2 QAa3
RAc
*Note 1
tCDL
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1 QAc2
CL=3
QAa0 QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1
WE
DQM
Row Active Read
(A-Bank) (A-Bank)
Precharge
(A-Bank)
Row Active
(B-Bank)
Write
(B-Bank)
Row Active
(A-Bank)
Read
(A-Bank)
: Don't care
*Note : 1. tCDL should be met to complete write.