K4S161622D Datasheet, PDF (5/41 Pages) Samsung semiconductor – 512K x 16Bit x 2 Banks Synchronous DRAM

K4S161622D
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V^*2, TA = 0 to 70°C)
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4 / 0.4
1.4
tr / tf = 1 / 1
1.4
See Fig. 2
3.3V
Output
870Ω
1200Ω
50pF^*2
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
CMOS SDRAM
Z0=50Ω
Unit
V
V
ns
V
Vtt=1.4V
50Ω
50pF^*1
(Fig. 1) DC Output Load Circuit
Note : 1. The DC/AC Test Output Load of K4S161622D-55/60/70 is 30pF.
2. The VDD condition of K4S161622D-55/60 is 3.135V~3.6V.
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
CAS Latency
CL
CLK cycle time
tCC(min)
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRCD(min)
Row precharge time
tRP(min)
Row active time
tRAS(min)
tRAS(max)
Row cycle time
tRC(min)
Last data in to row precharge
tRDL(min)
Last data in to new col.address delay
tCDL(min)
Last data in to burst stop
tBDL(min)
Col. address to col. address delay
tCCD(min)
Mode Register Set cycle time
tMRS(min)
Number of valid output data
CAS Latency=3
CAS Latency=2
-55
32
5.5 -
3-
3-
7-
10 -
-60
32
6-
3-
3-
7-
10 -
Version
-70
32
7 8.7
2
32
32
75
100
10 7
1
1
1
1
2
2
1
-80
32
8 10
-10
32
10 12
3 2 22
3 2 22
6 5 54
9 7 76
Unit
CLK
ns
CLK
CLK
CLK
CLK
us
CLK
CLK
CLK
CLK
CLK
CLK
ea
Note
1
1
1
1
1
2, 5
2
2
4
Notes : _{1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then}
rounding off to the next higher integer. Refer to the following clock unit based AC conversion table