K4S161622D Datasheet, PDF (39/41 Pages) Samsung semiconductor – 512K x 16Bit x 2 Banks Synchronous DRAM

K4S161622D
Self Refresh Entry & Exit Cycle
CMOS SDRAM
CLOCK
CKE
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
*Note 2
*Note 1
tSS
*Note 3
*Note 4
tRCmin
*Note 6
*Note 5
RAS
CAS
ADDR
*Note 7
BA
A10/AP
DQ
Hi-Z
Hi-Z
WE
DQM
Self Refresh Entry
Self Refresh Exit
Auto Refresh
: Don't care
*Note : TO ENTER SELF REFRESH MODE
1. CS, RAS & CAS with CKE should be low at the same clcok cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in self refresh mode as long as CKE stays "Low".
cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System colck restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.